Job Description and Requirements
Synopsys Inc. is looking for a full time candidate to work on the industry's leading and fastest emulation system, Zebu Server, which offers the industry's largest design capacity, supporting SOC chips as large as 10 billion gates based on high-density 16 nano-meter FPGA technology. In Zebu emulation flow, the design under test is partitioned into multiple parts, each of which is compiled into a low-level binary bit-stream that can be downloaded and run on an underlying FPGA in the emulation hardware.
Individuals that fill the position will work in a global multi-site team specializing in areas such as logic partitioning, placement and routing, pin assignment, static timing analysis, and timing performance optimization to design and develop the next generation emulation backend technologies used in Zebu software tools. The responsibilities include innovating good ideas to solve challenging practical problems, developing a software program based on the selected innovative idea, and demonstrating the effectiveness of it by running benchmarking designs and comparing the results.
Job requirements: BS/MS/Ph.D. Degree in Computer Science, Computer Engineering, or Electrical Engineering. Proficient in Verilog, Verilog 2001 or System Verilog Understanding of digital logic design, FPGA architecture, and hardware description language. Software development experience in developing and testing large C++ applications in Linux environment is preferred EDA knowledge preferred, especially in place-and-route, static timing analysis, synthesis or timing closure for large capacity and high-performance designs. Strong research and development capabilities, innovative problem-solving skills. Publications in EDA conference/journals are plus. Experience with efficient algorithm and data structure design. Highly developed interpersonal skills and the ability to work well either in a team-based environment or independently. Experience in the following area are highly desired: Block to module level architecture/spec definition and review Embedded processor RTL implementation High bandwidth/low latency/pipelined data channel, and switches RTL implementation Host interface and DMA processor RTL implementation IP usage, such as PCI Express controller, DDR3/4 controller, Multi Gigabit Transceiver, SerDes At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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Job Category
Engineering
Country
United States
Job Subcategory
R&D Engineering
Hire Type
Employee