Public Profile of Member Ravneet Kaur

Electronics
AND College,Delhi University, India

Interests

My research areas include analytical analysis, characterization and simulation of short channel effects in sub-100nm MOSFET for high performance. The work involves the physics based analytical modeling of MOS devices and simulating their intrinsic and terminal characteristics using numerical simulation software - ATLAS 2D and ATLAS 3D. The two-dimensional simulation and analytical modeling of sub-100nm gate-engineered Insulated Shallow Extension (ISE) devices and Grooved/ Concave Gate MOSFET for high performance RF and microwave applications has been done. My present research areas focus on the development of efficient 2D algorithms and optimization techniques for advanced sub-100nm MOS devices. Consideration has also been given to exploration of new architectures of Silicon on Insulator and Silicon On Nothing MOSFETs for enhanced performance and their applications in various different fields. Recently, I have started with modeling and simulations of HEMTs for high performance microwave circuits.
My initial work in 2007 was based on the development of a new simple and computationally efficient two-dimensional analytical model for various advanced channel engineered MOSFET structures such as Epi-layer, Graded channel (GC), Lightly doped drain (LDD), Halo, Pocket implant technology etc for channel lengths down to 90 nm gate length, incorporating the effect of DIBL. The subthreshold drain current model using Voltage Doping Transformation (VDT) method, replaced the influence of the lateral drain-source field by an equivalent reduction in the channel doping concentration.
In later part of 2007, a non-conventional MOSFET architecture of Insulated Shallow Extension (ISE) was studied. Substantial theoretical contributions had been made by developing compact models for Sub- 90 nm, ISE MOSFET for mixed mode applications. Electrical characteristics of 50nm DMG-ISE Gate stack MOSFET were investigated by extensive simulation studies using the non-local transport mechanisms of velocity overshoot and carrier diffusion due to electronic temperature gradients. By incorporating DMG architecture hot carrier reliability was improved and projects better linearity performance along with improvement in device intrinsic gain, voltage gain and Ion/Ioff ratio. Further, for improving the short channel behaviour of an ISE MOSFET, the use of gate stack consisting of a thin interfacial oxide layer and High k layer has also been envisaged.

Publications

1. “Performance Investigation of 50nm Insulated Shallow Extension Gate Stack (ISEGaS) MOSFET for Mixed Mode Applications,” Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices, Vol. 54, No.2, pp. 365-368, February 2007.
2. “Hot carrier reliability and analog performance investigation of DMG-ISEGaS MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices Vol. 54, No. 9, pp. 2556-2561, September 2007.
3. “Unified Subthreshold Model for Channel Engineered Sub-100nm Advanced MOSFET Structures”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices , Vol. 54, No. 9, pp. 2475-2486, September 2007.
4. “Two-Dimensional Analytical Model to Characterize Novel MOSFET Architecture: Insulated Shallow Extension (ISE) MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Semiconductor Science and Technology, Vol. 22, pp. 952-962, 2007.
5. “Lateral Channel Engineered - Hetero Material Insulated Shallow Extension Gate Stack (HMISEGAS) MOSFET Structure: High Performance RF Solution for MOS Technology”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Semiconductor Science and Technology Vol. 22, pp. 1097-1103, 2007.

2008

6. “Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET For ULSI”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Micro Electronic Engineering, Vol. 85, No. 3, pp. 566-576, March 2008.
7. “Two-Dimensional Analytical Sub-Threshold Model of Multi-Layered Gate Dielectric Recessed Channel (MLaG-RC) Nanoscale MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, Vol. 23, No.4, 045006 (10pp), April 2008.
8. “Intermodulation Distortion and Linearity Performance Assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC Design”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Superlattices and Microstructures, Vol. 44, No.2, pp 142-153, August 2008.
9. “Investigation of Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) Sub-50nm MOSFET: A Novel Design”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Journal of Numerical Modeling: Electronic Networks, Devices and Fields (Accepted July 2008).
10. “TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its Multi-Layered Gate Architecture: Part-I: Hot Carrier Reliability Evaluation”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 10, pp. 2602-2613, October 2008 .
11. “On-State and RF Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic and Switching Applications”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, Vol. 23, No.9, 095009, September 2008 .
12. “Modeling and Analysis of fully strained and partially relaxed lattice mismatched AlGaN/GaN HEMT for High Temperature Applications”, Parvesh Gangwani, Ravneet Kaur, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R.S. Gupta, Superlattices and Microstructures, Vol. 44, No.6, pp 781-793, December 2008.

2009

13. “Two-Dimensional Analytical Modeling of a Novel Gate-Stack ISE MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Micro Electronic Engineering , Vol. 86, Issue 10, pp 2005-2014, October 2009.
14. “Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, Vol.24, 10pp, 2009..
15. “TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Superlattices and Microstructures, Volume 46, Issue 4, Pages 645-655, October 2009.
16. “T-gate Geometric (Solution for Submicrometer Gate Length) HEMT: Physical Analysis, Modeling and Implementation as Parasitic Elements and its usage as Dual Gate for Variable Gain Amplifiers”, Ritesh Gupta, Servin Rathi, Ravneet Kaur, Mridula Gupta and Radhey S Gupta, Superlattices and Microstructures, Volume 45, Issue 3, Pages 105-116, March 2009.

2010

17. “Hot Carrier Reliability Monitoring of DMG ISE SON MOSFET for Improved Analog Performance”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Microwave and Optical Technology Letters, Vol.52, No.3, pp. 770-775, 2010.
18. “Design Considerations and Impact of Technological Parametric Variations on RF/Microwave Performance of GEWE-RC MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Microwave and Optical Technology Letters, Vol.52, No.3, pp.652-657, 2010.
19. “Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications”, Ritesh Gupta, Ravneet Kaur, Sandeep Kr Aggarwal, Mridula Gupta and R. S. Gupta, Journal of Semiconductor Technology and Science, Vol.10, No.1, Pages 66-76, March, 2010.

International Conferences
2005
1. “Investigating the role of Stacked Gate Oxide and Hetro-Material Gate on Electrical Characteristics of Insulated Shallow Extension (ISE) MOSFET”, Ravneet Kaur, Manoj Saxena and R. S. Gupta, Thirteenth International Workshop on Physics of Semiconductor Devices (IWPSD-2005), Vol. 2, pp 1163-1166, 13-17 December 2005,New Delhi India.

2006

2. “Gate Oxide Engineered Dual Material Gate Insulated Shallow Extension (GOXDMG-ISE) MOSFET: A New Vent to Wireless Communication”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, 3rd International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, university of Calcutta, pp. 324-327, December 18-20, 2006.
3. “Exploration of the Effect of Negative Junction Depth on the Electrical Characteristics of Concave DMG MOSFET in Sub-50-Nanometer Regime”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, 3rd International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, university of Calcutta, pp. 317-319, December 18-20, 2006.

2007

4. “Nanoscale Insulated Shallow Extension MOSFET with Dual Material Gate for High Performance Analog Operations” , Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) Mumbai, pp.171-173, December 16-20, 2007.
5. “Subthreshold Performance Consideration of a Novel Architecture: ISEGaS deca-nanometer MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) Mumbai, pp.123-126, December 16-20, 2007.
6. “RF-Distortion in Sub-100nm L-DUMGAC MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) Mumbai, pp.168-170, December 16-20, 2007.
7. “Two-Dimensional Analytical Threshold Voltage Model for Nanoscale SG-Concave MOSFET in Sub-50nm Regime”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) , Mumbai, India, pp.221-224, December 16-20, 2007.
8. “Linearity Assessment in DMG ISEGaS MOSFET for RFIC Design”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Nineteenth Asia Pacific Microwave Conference, APMC 2007, pp.2495-2498, December 11-14, 2007, Bangkok, Thailand.
9. “Electrical Characterization of Insulated Shallow Extension (ISE) MOSFET: A Punchthrough Stopper”, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, 11th International Symposium on. Microwave and Optical Technology (ISMOT 2007) Villa Mondragone, Monte Porzio Catone, Italy, pp.813-816, 17-21 December 2007.
10. “Pre-Distortion Linearity Enhancement for Sub-50nm Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET”, Rishu Chaujar, Ravneet Kaur, Mridula Gupta, Manoj Saxena, Mridula Gupta and R. S. Gupta, 11th International Symposium on. Microwave and Optical Technology (ISMOT 2007), pp.797-800, 17-21 December 2007.
11. “Two-Dimensional Simulation of C-V Characteristics of Deep Submicron AlmGa1-mN/GaN HEMT for Microwave Applications” , Parvesh Gangwani, Ravneet Kaur, Sujata Pandey , Subhasis Haldar, Mridula Gupta and R. S. Gupta, 11th International Symposium on. Microwave and Optical Technology (ISMOT 2007) pp.33-36, 17-21 December 2007.
12. “On-State and Switching Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic Applications”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Semiconductor Device Research Symposium (ISDRS 2007 ) University of Maryland, USA,pp.1892-1893, December 12-14, 2007.
13. “2-Dimensional Simulation and Characterization of Deep Submicron AlGaN/GaN HEMTs for High Frequency Applications”, Parvesh, Ravneet Kaur, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R. S. Gupta, International Semiconductor Device Research Symposium (ISDRS 2007 ), University of Maryland, USA,pp.1892-1893, December 12-14, 2007.
14. “Dual Material Gate (DMG) SOI-MOSFET with Dielectric Pockets: Innovative Sub-50 nm design for improved switching performance”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007), pp. 109, December 19–21, 2007, New Delhi, India.
15. “Two-Dimensional Analytical Modeling and Simulation of Rectangular Gate Recessed Channel (RG-RC) Nanoscale MOSFET in Sub-50nm Regime”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007), pp.110, December 19–21, 2007, New Delhi, India.

2008

16. “Nanoscale Analytical Modeling and TCAD Simulations of a Novel Gate Dielectric Stack SDPI MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Communicated to 2nd IEEE International Nanoelectronics Conference (INEC-2008), March 24-27, 2008, Shanghai, China (Accepted).
17. “TCAD Investigation of Hot Carrier Reliability Issues Associated with GEWE-RC MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta Communicated to 2nd IEEE International Nanoelectronics Conference (INEC-2008), March 24-27, 2008, Shanghai, China (Accepted).
18. “Sub-Threshold Drain Current Performance Assessment of MLGEWE-RC MOSFET for CMOS Technology”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 27-28, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
19. “RF Performance Assessment of L-DUMGAC MOSFET for Future CMOS Technology in GigaHertz Regime”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 29-30, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
20. “TCAD Investigation of a Novel MOSFET Architecture of DMG ISE SON MOSFET for ULSI Era”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 18-19, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
21. “Analytical Analysis of Sub-Threshold Performance of Sub-100nm Advanced MOSFET Structures-An Iterative Approach”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 20-21, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
22. “Modeling of nitride based Hetrojunction Transistors for RF Applications” , Parvesh, Ravneet Kaur, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Mini-Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed mode Applications-2008, pp. 35-36, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
23. “Temperature Dependent Analytical Model of AlGaN/GaN HEMT” , Parvesh, Ravneet Kaur, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Mini-Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed mode Applications-2008, pp. 37-38, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
24. “Pre-Distortion Assessment of Workfunction Engineered Multi-Layer Dielectric Design of DMG ISE SON MOSFET”, R.Kaur, R.Chaujar, M.Saxena, M.Gupta and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show - Nanotech 2008, 11th International Conference on Modeling and Simulation of Microsystems (MSM-2008), Vol. 3, pp. 605-606, June 1-5, 2008, Boston, Massachusetts, U.S.A..
25. “An Iterative Approach to Characterize Various Advanced Non-Uniformly Doped Channel Profiles”, R.Kaur, R.Chaujar, M.Saxena, M.Gupta and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show - Nanotech 2008, 2008 Workshop on Compact Modeling (WCM-2008), Vol. 3, pp. 814-817, June 1-5, 2008, Boston, Massachusetts, U.S.A..
26. “Compact Analytical Threshold Voltage Model for Nanoscale Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) MOSFET”, R.Chaujar, R.Kaur, M.Saxena, M.Gupta and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show - Nanotech 2008, 2008 Workshop on Compact Modeling (WCM-2008), Vol. 3, pp. 873-876, June 1-5, 2008, Boston, Massachusetts, U.S.A. .
27. “Assessment of L-DUMGAC MOSFET for High Performance RF Applications with Intrinsic Delay and Stability as Design Tools”, R.Chaujar, R.Kaur, M.Saxena, M.Gupta and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show - Nanotech 2008,11th International Conference on Modeling and Simulation of Microsystems (MSM-2008), Vol. 3, pp. 586-589, June 1-5, 2008, Boston, Massachusetts, U.S.A. .
28. “Impact of Multi-Layered Gate Design on Hot Carrier Reliability of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET”, R.Chaujar, R.Kaur, M.Saxena, M.Gupta and R. S. Gupta, XXIX General Assembly of the International Union of Radio Science (Union Radio Scientifique Internationale-URSI), Illinois, USA, August 07-16, 2008.
29. “GEWE-RC MOSFET: A Solution to CMOS Technology for RFIC Design Based on the concept of Intercept Point”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S.Gupta, International Conference on Recent Advancements in Microwave Theory and Applications (Microwave-2008), pp. 661-663, Jaipur, India, November 21-24, 2008.
30. "Impact of Gate Stack Configuration onto the RF/analog Performance of ISE MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, International Conference on Recent Advancements in Microwave Theory and Applications (Microwave-2008), pp. 686-688, Jaipur, India, November 21-24, 2008.
31. “Analytical Approach for High Temperature Analysis of AlGaN/GaN HEMT”, Parvesh, Ravneet Kaur, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R. S. Gupta, International Conference on Recent Advancements in Microwave Theory and Applications (Microwave-2008), pp. 725-728, Jaipur, India, November 21-24, 2008.
32. “TCAD Performance Investigation of a Novel MOSFET Architecture of
Dual Material Gate Insulated Shallow Extension Silicon On Nothing (DMG ISE
SON) MOSFET for ULSI era,” Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Asia Pacific Microwave Conference (APMC-2008), December 16-20, 2008, Hongkong, China
33. “GEWE-RC MOSFET: High Performance RF Solution to CMOS Technology”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S.Gupta, Asia Pacific Microwave Conference (APMC-2008), December 16-20, 2008, Hongkong, China.
34. “Capacitance modeling of 120nm AlGaN/GaN HEMT for microwave and high
speed circuit applications,” Parvesh, Ravneet Kaur, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Asia Pacific Microwave Conference (APMC-2008), December 16-20, 2008, Hongkong, China.

2009

35. “Analytical Drain Current Evaluation Technique for Various Non-Uniformly Doped MOS Device Architectures”, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Symposium on Microwave and Optical Technology (ISMOT) – 2009, December 16-19,2009 in Hotel Ashok, New Delhi, India.

National Conferences:
2006

1. “RF Performance Investigation of Gate Stacked Insulated Shallow Extension (ISE) MOSFET and Bulk: A Comparative Study,” Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 254-258, 24-26 March 2006, New Delhi, India.
2. “Lateral Channel Engineered Structure- Insulated Shallow Extension (ISE) MOSFET: DC and RF Performance Investigation”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 119-122, 6-8 October 2006, Jaipur, India.
3. “Design and FPGA realization of Direct Sequence-Spread Spectrum (DS-SS) BPSK Modulator using a Five Stage Gold Code Generator”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 213-216, 24-26 March 2006, New Delhi, India.
4. “Exploring the Effect of Negative Junction Depth on Electrical Behaviour of Sub-50-Nanometer Concave DMG MOSFET: A Simulation Study”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 123-125, 6-8 October 2006, Jaipur, India.
5. “Scrambled Sequence FPGA based Direct Sequence Spread Spectrum BPSK Modulator: 10 Stage Analysis”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Recent Trends in Electronics and Information Technology, (RTEIT 2006), pp 334-337, 28-29 July 2006, Kopargaon Maharashtra, India.

2007

6. “Effect of transport property on the performance of insulated shallow extension gate stack (ISEGaS) MOSFET", Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, August 17-18, 2007, pp. 52-57, Panjab Engineering College, Chandigarh, India.
7. “New Concave MOSFET with Transverse Dual Material Gate (T-DMG) in Sub-50nm Regime: A Simulation Study", Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Indian Microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, August 17-18, 2007, pp. 33-37, Panjab Engineering College, Chandigarh, India. (Best Student Paper Award)

2008

8. “Development Board-Level Experimentation and Simulation of FPGA based DEBPSK DSSS Modulator: Implementation of 10-Chip Gold Code Sequence Generator”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008), pp. 255- 261, September 26-28, 2008 in New Delhi, India.
9. “Simulation of a Novel ISE MOSFET with Gate Stack Configuration”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008), pp. 291-296, September 26-28, 2008 in New Delhi, India.
10. “High Temperature Performance of AlGaN/GaN HEMT”, Parvesh, Ravneet Kaur, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R S Gupta, Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008), pp. 305-308, September 26-28, 2008 in New Delhi, India.
11. “Experimental Investigation of Emergency Siren Simulator for Real-Time Small-Signal Power Applications”, Rajat, Prince, Anju Agrawal, Rishu Chaujar and Ravneet Kaur, 2nd National Workshop on Advanced Optoelectronic Materials and Devices (AOMD 2008), December 22-24, 2008, Department of Electronic Engineering, Institute of Technology, Banaras Hindu University, Varanasi, India.
12. “Solution to CMOS Technology for High Performance Analog Applications: GEWE-RC MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, 2nd National Workshop on Advanced Optoelectronic Materials and Devices (AOMD 2008), December 22-24, 2008, Department of Electronic Engineering, Institute of Technology, Banaras Hindu University, Varanasi, India.