Publications
Refereed Journal Publications
1. Jebashini Ponnian, Senthilpari, R.Uma, Ooi Chee Pun, An Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm, Accepted in Emerging Science Journal . Q1
2. Nagisetty Sridhar, C Senthilpari, Mardeni R, Wong Hin Yong, Design of An Active element-based Class-J Power Amplifier for 5G Wireless Communication Applications,resmilitaris, , Vol. 13 No. 2 (2023): Volume 13, Number 2, 2023. Scopus
3. Ponnian, J., Pari, S., Ramadass, U., Pun, O.C. (2023). A Unified Libraries for GDI Logic to Achieve Low-Power and High-Speed Circuit Design. In: Shetty, N.R., Patnaik, L.M., Prasad, N.H. (eds) Emerging Research in Computing, Information, Communication and Applications. Lecture Notes in Electrical Engineering, vol 928. Springer, Singapore. https://doi.org/10.1007/978-981-19-5482-5_36.Q4
4. Vishnupriya Shivakumar, C. Senthilpari, Zubaida Yusoff, (2022) “Test power and area optimized logic built-in self-test with higher fault coverage for automobile SoCs, Microelectronics Journal, Volume 124,2022,105430,https://doi.org/10.1016/j.mejo.2022.105430. Q2
5. C Senthilpari, R Deena, L Lini (2022) Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders, F1000Research 11 (7), 7 Q1.
6. Nagisetty Sridhar, C. Senthilpari, R. Mardeni, Wong Hin Yong , T. Nandhakumar, A low power, highly efficient, linear, enhanced wideband Class‑Jmode power amplifier for 5G applications, Scientific Reports | (2022) 12:8101 | https://doi.org/10.1038/s41598-022-12235-z Q1
7. N Sridhar, C Senthilpari, R Mardeni, WH Yong An enhanced broadband class-J mode power amplifier for 5G smart meter applications, F1000Research 10 (1099), 1099. Q1
8. S.Deivasigamani, G.Narmadha, P.K.Rajesh, C.Senthilpari, Wong Hin Yong, Epileptic E.E.G. signal classifications based on DT-CWT and SVM classifier, Journal of Engineering Research, pp 1-1 Q3.
9. K. Diwakar, C. Senthilpari, V. V. Rajasegharan, S. Immanuel Ebenezer ‘ROLE OF ‘e’ IN ENGINEERING APPLICATIONS, accepted, in JESTEC, Vol. 16, No. 6 (2021) 4612 – 4625. Q3
10. C.Senthilpari, P. Velrajkumar, Diwakar, Joseph Sheela Francisca, Design A Low Power And High Throughput Error Detection And Data Correction Architecture By Razor II Method, PalArch’s Journal of Archaeology of Egypt/Egyptology 17 (9),2020, 4393-4410 Q3.
11. VISHNU PRIYA SHIVAKUMAR, C. SENTHILPARI, Zubaida Yusoff, A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture, IEEE Access 9, 2021, 29366-29379 Q1. DOI: 10.1109/ACCESS.2021.3059171
12. Vishnupriya Shivakumar, C. Senthilpari, Zubaida Yusoff, DCVS design and analysis of the LFSR using feedback polynomial function for its low-power and reduced area overhead, Solid-state technology, Vol. 63 No. 4 (2020), pp 7219- 7229 Q4.
13. Sathya Priya, P Velrajkumar, J Joyce Jacob, C Senthilpari, Development of Six Axes Robotic Arm Manipulator using Android Application, Solid State Technology 63 (6), 2020, pp 8082-8089 Q4.
14. Jebashini Ponnaian, C.Senthilpari, Uma Ramadass, Ooi Chee Pun “A New Systematic GDI Circuit Synthesis Using MUX Based Decomposition Algorithm and Binary Decision Diagram for Low Power ASIC Circuit Design” Microelectronics Journal, Vol 108, 2021, pp 104963 Q2.
15. V Shivakumar, C Senthilpari, Z Yusoff Design of a 1.9 GHz low-power LFSR circuit using the Reed-Solomon algorithm for Pseudo-Random Test Pattern Generation, International Journal of Integrated Engineering 13 (6), 220-232.Q3.
16. C.Senthilpari, Gautam, K.Diwakar, P.Velrajkumar Sedia, R. Balachandran ‘ Thermal Sensor Circuit for 5G Wireless Technology, Solid State Technology Vol. 63 (1), 2020, pp 11-21 Q4.
17. S Deivasigamani, C.Senthilpari, Wong Hin Yong “Machine learning method-based detection and diagnosis for epilepsy in E.E.G. signal Journal of Ambient Intelligence and Humanized Computing 12 (3), 4215-4221. 2021, https://doi.org/10.1007/s12652-020-01816-3Q3
18. V.Chitra P.Velrajkumar, P.Ramesh, C.Senthilpari, T.Bhuvaneswari ‘Development Of Autonomous Robot For Tunnel Mapping Using Raspberry Pi Processor INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH, Vol 9 Issue 3, 2020, pp 191-194. Scopus
19. D Kodandapani P Velrajkumar, C.Senthilpari, P Ramesh, G Ramanamurthy Development of Smart Number Writing Robotic Arm using Stochastic Gradient Descent Algorithm International Journal of Innovative Technology and Exploring Engineering, Vol 8, issue 10, 2019, 542 – 547. Scopus
20. Velrajkumar Pitchandi, Senthilpari Chinnayan, Sheela Francisca Joseph, Nirmal Raj Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks, International Journal of Electronics and Telecommunications, Vol.65, (3), 2019, pp 477-483. Q3.
21. ROSALIND DEENA KUMARI SELVAM, C. SENTHILPARI, LEE LINI, DESIGN OF A 16-BIT ADDER FOR DECODER APPLICATION CIRCUIT Journal of Engineering Science and Technology, Special Issue on SU18, February (2019) 249 - 260.Q2
22. S Deivasigamani, C Senthilpari, Hin-Yong Wong Computer-Aided Automatic Detection and Classification of E.E.G. Signals for Screening Epilepsy Disorder JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 34 (3), (2018) pp 687-700. Q2
23. T.NIRMALRAJ, SK.PANDIAN, C.SENTHILPARI Low power and improved speed 1T dram using dynamic logic- Journal of Engineering Science and Technology 13 (6), (2018) 1636-1650. Q2.
24. Rosalind Deena Kumari, C. Senthilpari, Lee lini, Improved speed low power and low voltage SRAM design for LDPC application circuits - Journal of Engineering Science and Technology Vol. 13, No. 3 (2018) 822 – 837. Q2
25. C.Senthilpari, K. Diwakar, Kumar Munusamy, J. Sheela Francisca “Layout parameter analysis in Shannon expansion theorem based on 32-bit adder circuit” Engineering Science and Technology, an International Journal 20 (2017) 35–40. Q1
26. S. Deivasigamani, C. Senthilpari, Wong Hin Yon “Classification of focal and nonfocal E.E.G. signals using ANFIS classifier for epilepsy detection” International Journal of Imaging Systems and Technology, Volume 26, Issue 4, December 2016, Pages 277–283. Q2
27. T.Nirmalraj, S.K.Pandian and C.Senthilpari “Low power dual-stack in MTCMOS circuits using dynamic logic and sleep transistor techniques” Far east journal of electronics and communications- special issues (march 2016) pp-2016. Q3
28. JE Raja, WS Lim, C Venkataseshaiah, C Senthilpari, S Purushothaman “Need for Adaptive Signal Processing Technique for Tool Condition Monitoring in Turning Machines Asian Journal of Scientific Research 9 (1), 1, 2016, pp 1-12. Q4
29. P Velrajkumar, C Senthilpari, GR Murthy, EK Wong, Low Energy, Improved Speed, and High Throughput CORDIC Cell to Improve Performance of Robots’ Processor” Asian Journal of Scientific Research 8 (3), 2015, pp381-391. Q4
30. P.Velrajkumar*, C.Senthilpari, G.Ramanamurthy, E.K. Wong “Design of Low EPI and High Throughput CORDIC cell to improve the performance of Mobile Robot” Journal of Engineering Science and Technology Vol. 9, No. 2,2014. pp 167 – 175. Q2
31. K. Diwakar, K. Aanandha Saravanan, C. Senthilpari, Stable Delta-Sigma Modulator with Signal Dependent Forward Path Gain for Industrial Applications World Academy of Science, Engineering and Technology International Journal of Electrical, Computer, Electronics, and Communication Engineering Vol:8 No:9, pp1432-1435. 2014. Scopus
32. K. Diwakar, N. Vasudevan, C. Senthilpari “MOSFET Based A.D.C. for Accurate Positioning of Control Valves in Industry” World Academy of Science, Engineering and Technology International Journal of Electrical, Electronic Science and Engineering Vol:8 No:1, pp, 1-5 2014.
33. C. Senthilpari, Rosalind Deena Kumari, K. Diwakar Velraj Kumar, G. Ramanamurthy., Low Power and 5.8 GHz Operating Frequency of Digital Frequency Divider Using Proposed Sequential Circuit. Aust. J. Basic & Appl. Sci., 8(1): 273-281, 2014
34. K.Diwakar, N. Vasudevan., C. Senthilpari., Multi-Phase Switching Converters with Extended Range Multi-Inputs. Aust. J. Basic & Appl. Sci., 7(12): 68-73, 2013.
35. G. Ramana Murthy, C. Senthilpari, P. Velrajkumar, Lim Tien Sze “Design of Low Power and High-Speed Digital I.I.R. Filter in 45nm with Optimized C.S.A. for Digital Signal Processing Applications” World Academy of Science, Engineering and Technology International Journal of Computer, Information Science and Engineering Vol:7 No:4, pp 164-171, 2013.
36. P.Velrajkumar, C.senthilpari, G.Ramana Murthy and E.K Wong “Proposed adder and Modified L.U.T. bit parallel Unrolled CORDIC circuit for an application in mobile Robots” Asian Journal of Research 6(4): 666-678,2013. Scopus
37. Ramana Murthy, G., Senthilpari, C., Velrajkumar, P. and Tien Sze, L. (2014), "Monte-Carlo analysis of a new 6-T full-adder cell for power and propagation delay optimizations in 180 nm process", Engineering Computations, Vol. 31 No. 2, pp. 149-159. https://doi.org/10.1108/EC-01-2013-0023.
38. G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze “A Novel Design of Multiplexer Based Full-Adder Cell for Power and Propagation Delay Optimizations” Journal of Engineering Science & Technology, Vol. 8, No. 6 (2013) 764 - 777. Q2.
39. Bhuvaneswari, T., Prasad, V., Singh, A. K. and Senthilpari, C., Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis. Int. J. Circ. Theory Application. Volume 41, Issue 8, pages 844–853, August 2013.Q2 (S.C.I. indexed)
40. C. Senthilpari, P. Velrajkumar, G. Ramana Murthy, and J. Emerson raja “Low-Power, High Throughput unsigned Multiplier using Modified C.P.L. Adder cell” Australian Journal of Basic and Applied Sciences, 6(12): 123-130, 2012.
41. G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze “ A new 6-T multiplexer based full adder for low power and leakage current optimization” ICICE Electronics Express vol.9, No17, pp1434-1441, 2012. Q3
42. Pitchandi Velraj Kumar, C.Senthilpari, G.Ramana Murthy and E.K Wong “Bit-parallel iterative circuit for robotic application” ICICE Electronics Express Vol.9. No.6. pp.443- 449, 2012. Q3
43. G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze “Interconnect Analysis of a Novel Multiplexer Based Full-Adder Cell for Power and Propagation Delay Optimizations” International Journal of Electronics and Electrical Engineering Vol.6 2012 pp 299-303.
44. C.Senthilpari, G.RamanaMurthy, P.Velrajkumar “An Efficient EPI and Energy Consumption of 32 bit ALU using Shannon theorem based adder approach” Transaction of electronics WSEAS, ISSN: 1109-2734, Issue 7, Volume 10, July 2011, pp: 231-238.
45. C.Senthilpari “A Low Power and High-Performance Radix-4 Multiplier Design Using a Modified Pass-Transistor Logic Technique” IETE Journal of Research, Vol. 57, Issue 2, pp 149-155, 2011.Q3
46. C Senthilpari, ZI Mohamad, S Kavitha Proposed low power, high speed adder-based 65-nm Square root circuit, Microelectronics Journal 42 (2), 2011, 445-451. Q3
47. K.Diwakar, C.Senthilpari, Ajay Kumar Singh, Lim Way Soong. Vector Quantized Signal Dependent Delta-Sigma Modulator Based High-Performance Three-phase Switching Converter. IEICE Electronics Express, Vol.6, no.17, 1259-1265, 2009. Q3
48. K. Diwakar, C.Senthilpari, Ajay Kumar Singh and Lim way Soong “Delta- Sigma Modulator based analog multiplier with Digital output” Recent Patents on Electrical Engineering 2009, 2, 161-164. Q1
49. K. Diwakar, C.Senthilpari, Ajay Kumar Singh and Lim way Soong “Delta-sigma modulator based multipliers” IEICE Electron. Express, Vol. 6, No. 6, pp.322 -328, (2009). Q3
50. K. Diwakar, C.Senthilpari, and Ajay Kumar Singh “Highly Stable and Wide Input Delta-Sigma A.D.C. for the Precise Control of Stepper Motors Operating as Actuators of Control Valves in Industry” European Journal of Scientific Research, ISSN 1450-216X Vol.22 No.1 (2008), pp.6-15.
51. C.Senthilpari, Ajay Kumar Singh and K.Diwakar “An Efficient 16-bit Non-Clocked Pass Gates Adder Circuit with Improved Performance on Power Constraint” European Journal of Scientific Research, ISSN 1450-216X Vol.28 No.3 (2009), pp.451-461.
52. C.Senthilpari, Ajay Kumar Singh and K.Diwakar “Low power, Low latency, high throughput 16-bit C.S.A. adder using Non clocked pass transistor Logic” Journal of circuits systems and computers Volume 18, No.3 May 2009, pp 581-596. Q3
53. C.Senthilpari, Ajay Kumar Singh and K.Diwakar “Low Energy, Low Latency and High-Speed Array Divider Circuit Using a Shannon Theorem Based Adder Cell” Recent Patents on Nanotechnology 2009, Vol. 3, pp.61-72. Q1
54. K. Diwakar, C.Senthilpari, and Ajay Kumar Singh, “Highly stable Delta-Sigma Modulator for industrial applications”, IEICE Electron. Express, Vol. 5, No. 15, pp.530-536, (2008). Q3
55. C.Senthilpari, Ajay Kumar Singh and K.Diwakar “Effect of scaling on the performance of the 4-bit C.P.L. subtractor circuit” European Journal of Scientific Research ISSN 1450-216X Vol.20 No.2 (2008), pp.239-248.
56. C.Senthilpari, Ajay Kumar Singh and K.Diwakar “Design of a low power, high performance, 8x8 bit multiplier using a Shannon-based adder cell” Microelectronics Journal 39 (2008) 812–821.
Conference Paper
1. C.Senthilpari, K.Diwakar, Deivasiganmani, Velrajkumar and Rajendren ayyavoo “ Power Efficiency Top-Down ALU for Error Correction and Detection Circuit- IEEE conference, Proceedings of Third IEEE International Conference on Communication, Computing & Industry 4.0 (C2I4) - 2022ISBN : CFP22Y51-DVD 978-1-6654-7496-2; XPLORE : CFP22Y51-ART 978-1-6654-7497-9
2. Rosalind deena Kumari, Senthilpari, Lee Lini and Deiva sigamani (2022)" Low power and High speed decoder circuit using LDPC codes; Ninth international conferences on the advances in information technology and networking (ICATN. 22).
3. V ShivaPMSathya, P Velrajkumar, P Lavanya, L Ramesh, C Senthilpari,(2022), Raspberry PiProcessor-based i-Gloves for Mute Community and Home Automation System, 20228th International Conference on Smart Structures and Systems (ICSSS), 01-05.
4. C.SenthilPari, Maufuz Imran, T.Nirmal Raj, P.VelrajKumar (2018), Design a Low voltage & Low power multiplier-free pipelined D.C.T. architecture using full hybrid adder- accepted 5th IEEE ICETAS 2018.
5. Rosalind Deena Kumari selvam, C. Senthilpari, Lee lini (2018), DESIGN OF A 16-BIT ADDER FOR DECODER APPLICATION CIRCUIT- Accepted in Eureka conference Taylors university 2018.
6. T.Nirmalraj, S.K.Pandiyan C.Senthilpari LOW POWER AND IMPROVED SPEED 1T DRAM USING DYNAMIC LOGIC, ICRECT Conference proceedings, 8-10 Sept 2016.
7. S. Deivasigamani, C. Senthilpari, Dr.Wong Hin Yong, Computer-Aided Automatic Detection and Classification of E.E.G. Signals for Screening Epilepsy Disorder, ICRECT Conference proceedings, 8-10 Sept 2016.
8. Rosalind Deena Kumari Selvam, C. Senthilpari, Lee Lini “Low power and low voltage SRAM design for LDPC codes hardware applications” IEEE-ICSE2014 Proc. 2014, Kuala Lumpur, Malaysia, pp 332-335.
9. Kumar Munusamy, C.Senthilpari and Daniel C.K. Kho “A low power hardware implementation of S-Box for Advanced Encryption Standard” 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 11th International 2014.
10. J. Emerson Raja, W. S. Lim, C. Venkataseshaiah, C. Senthilpari, M. N. Ervina Efzan “Tool Wear Classification by Acoustic Analysis using Adaptive Signal Processing Technique” ICEIC conference 2014.
11. C.Senthilpari, Velrajkumar and RamanaMurthy “A high operating frequency 65nm digital frequency divider for multimedia applications” M.A.L. technical & Innovation Symposium in Infineon Melaka 2012.
12. G.Ramana Murthy, C.Senthilpari, T.S.Lim, P.Velrajkumar “Leakage current reduction of novel multiplexer based full- adder cell in CMOS 0.13µm technology”, TENCON 2011 IEEE pp. 734-738.
13. T. Bhuvaneswari, C. Senthilpari, Hii Ming Tat “Low Leakage and Low Power of CMOS SRAM Peripheral Circuit” IEEE Fukuoka TENCON 2010.
14. C.Senthilpari, S.Kavitha, Jude Joseph (2010) “Lower Delay and Area Efficient Non-Restoring Array Divider by using Shannon based Adder Technique” IEEE, ICSE2010 Proc. 2010, Melaka, Malaysia.
15. C.Senthilpari, K.M.Diwakar, Ajay Kumar Singh (2009). High Speed and High Throughput, 8x8 Bit Multiplier, Using a Shannon-Based Adder Cell.TENCON 2009 (International Technical Conference of IEEE), Singapore, 23-26 November 2009.
16. K. Diwakar, C.Senthilpari, Ajay Kumar Singh and Lim way Soong “Analog multiplier with high accuracy” IEEE conference ICSYN 2009 proce.2009, Indore, India.
17. K. Diwakar, C.Senthilpari and Ajay Kumar Singh “Switching Converter with Highly Stable Delta-Sigma Modulator” IEEE, ICSE2008 Proc. 2008, Johor Bahru, Malaysia, pp.11-17.
18. Wong Kiat Teong, Woon Tian Song, Wong Jia Hao, Jude Joseph and C.Senthilpari “Low power, low latency and area-efficient array multiplier using Complementary Pass Transistor Logics adder cell” R.S.M. 2007 Proc.2007, Penang, Malaysia, pp 90-94.
19. Wong Jia Hao, Woon Tian Song, Wong Kiat Teong, Jude Joseph and C. Sentilpari “Low Power and High-Performance High Radix Multiplier” R.S.M. 2007 Proc.2007, Penang, Malaysia, pp 84-89.
20. Jude Joseph, Woon Tian Song, Wong Jia Hao, Ricky Wong Kiat Teong, and C.Sentilpari “Lower delay and area-efficient Non restoring array divider by using Controlled add/subtract cells” R.S.M. 2007 Proc.2007, Penang, Malaysia, pp 24-28.
21. Woon Tian Song, Wong Jia Hao, Ricky Wong Kiat Teong, Jude and C.Sentilpari “ Low power and High-performance array shared multiplier using Complementary Pass Transistor Logics adder cell” R.S.M. 2007 Proc. 2007, Penang, Malaysia, pp 95-100.
22. C.Senthilpari, Ajay K S, K.Diwakar. Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic IEEE International Conference on Intelligent & Advanced Systems (ICIAS) ISBN: 1-4244-1356-7. 2007; pp: 1374 – 1378.
23. C.Senthilpari, Ajay Kumar Singh and A.Arokiasamy “Statistical analysis of Power Delay Estimation in adder circuit using non-clocked pass gate families” IEEE 4th International Conference on Electrical and Computer Engineering ICECE 2006, 19-21 December 2006, Dhaka, Bangladesh, pp-509-513.
24. C.Senthilpari, K.Diwakar, and Ajay Kumar Singh “ Power Deduction in Digital Signal Processing Circuit using Inventive C.P.L. Subtractor Circuit” IEEE, ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia, pp. 820-824.
Book Chapter:
1. C.Senthilpari “Low Power Arithmetic circuit design for multimedia Applications- I.G.I. Design and Modelling of low power VLSI design (chapter 10) 2016, pp 252-282.
2. C.Senthilpari, Hashyvin Arumugam, DESIGN A IOT GREENHOUSE MONITORING SYSTEM, Book Chapter MMU Press-