Publications
1. H. Elahipanah, “Record Gain at 3.1 GHz of 4H-SiC High Power RF MESFET,” Microelectron. J., vol. 42, no. 2, pp. 299–304, February 2011.
2. H. Elahipanah, “Simulation and optimization of high breakdown double-recessed 4H-SiC MESFET with metal plate termination technique,” Superlattices Microstructures, vol. 48, no. 6, pp. 529–540, December 2010.
3. H. Elahipanah and A. A. Orouji, “A 1300 V–0.34 Ω.cm2 Partial SOI LDMOSFET with Novel Dual Charge Accumulation Layers,” in press IEEE Trans. Electron Devices, vol. 57, no. 8, pp. 1959–1965, August 2010.
4. A. A. Orouji and H. Elahipanah, “A Novel Nanoscale 4H-SiC-on-Insulator MOSFET Using Step Doping Channel,” IEEE Trans. Dev. Mat. Rel., vol. 10, no. 1, pp. 92–95, March 2010.
5. H. Elahipanah and A. A. Orouji, “A Novel Step-Doping Fully-Depleted Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor for Reliable Deep Sub-micron Devices,” Jap. J. Appl. Phys., vol. 48, no. 11, October 2009.
6. A. Naderi, P. Keshavarzi, and H. Elahipanah, “The Impact of Varying Temperature on Performance of Carbon Nanotube Field-Effect Transistors,” in Proc. WSEAS, Italy, 2010.
7. H. Elahipanah and A. A. Orouji, “Novel Attributes in GaN Recessed-Gate MESFET with Narrow Channel Layer,” in 15th Int. Workshop Phys. Semiconductor Devices (IWPSD), Delhi, India, 2009, pp. 770–774.
8. H. Elahipanah and A. A. Orouji, “A Novel 1600-V 4H-SiC Lateral Pseudo-RESURF MOSFET with Dual Buried Layers Structure,” in Int. Symp. Compound Semiconductor, Japan, 2010.
9. H. Elahipanah, “Novel Attributes in GaN and 4H-SiC Recessed-Gate MESFETs for Small Signal Applications,” in Int. Symp. Compound Semiconductor, Japan, 2010.
