Publications
Book Chapters
1. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Effect of Independent Gate, Asymmetric and Gate-S/D Underlap features on Nano Scale Subthreshold Double Gate MOSFET Performance, Advances in Microelectronics and Photonics, Nova Science Publishers, 2011 (ISBN 978-1-61470-956-5).
International Journals
1. Vincent Pott, Ramesh Vaddi, Julius Tsai Ming Lin, and Tony T. Kim, " The shuttle nano-electro-mechanical non-volatile memory", IEEE Tran. on Electron Devices (Under Review).
2. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, “Analytical Subthreshold Potential Distribution Model for Gate Underlap Tied and Separated Double Gate MOSFETs with Symmetric, Asymmetric Options”, IEEE Tran. on Electron Devices (Under Review).
3. Ramesh Vaddi, R. P. Agarwal, S. Dasgupta, and T. Kim, "Design and Analysis of Double-gate MOSFETs for Ultra-low Power Radio Frequency Identification (RFID): Device and Circuit Co-design", Journal of Low Power Electronics and Applications, pp. 277-302, July 2011.
4. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal,” Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options," Elsevier Microelectronics Journal, Vol.42, Issue 5, pp.798-807, May 2011.
5. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, “Comparison of nano-scale complementary metal-oxide semiconductor and 3T–4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic“, Journal of IET Circuits, Devices & Systems , Vol. 4, Iss. 6, pp. 548–560, Nov.2010.
6. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, “Robustness Comparison of DG-FinFETs with Symmetric, Asymmetric, Tied and Independent gate options with circuit Co-Design for Ultra Low Power Subthreshold Logic", Elsevier Microelectronics Journal , Volume 41, Issue 4, pp. 195-211, April 2010.
7. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, “Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs," ASP Journal of Low Power Electronics (JOLPE) ,Vol. 6, No 1, pp.103-114, April 2010.
8. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal,” Device and Circuit Co-Design Robustness Studies in the Sub-threshold Logic for Ultra Low Power Applications for 32nm CMOS“, IEEE Tran. on Electron Devices,Vol.57, No.3,, pp.654-664, March 2010.
9. Ramesh vaddi, S. Dasgupta, R. P. Agarwal “Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultra- Low Power Applications”, VLSI Design Journal, Hindawi publishing corporation, New York, USA, Vol.2009, Article No. 1 ,Jan.2009 (DOI: 10.1155/2009/283702).
10. Madhavi Rani, Asha Jyothi, Anusha, Anil Kumar and Ramesh Vaddi “Digital Design and Simulation of a Minimum Size FIR Processor”, GITAM Journal of Information Communication Technology (GJICT), 2008.
International Conferences/Workshops:
1. Ramesh Vaddi, Vincent Pott, Julius Tsai Ming Lin, and Tony T. Kim, "Verilog-A modeling of an anchorless electro-mechanical non-volatile memory", Proc.17th Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, Jan,30-Feb,2, 2012 (Submitted).
2. Ramesh Vaddi and Tony T. Kim"Ultra-low Power High Efficient Rectifiers with 3T/4T Double-gate MOSFETs for RFID Applications", Proc.IEEE International Symposium on Integrated Circuits (ISIC), Singapore, Dec 12-14, 2011 (Accepted).
3. Ramesh Vaddi, S. Dasgupta, and R.P. Agarwal, " Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET", Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IIT Madras, India", pp.37-42, July 4-6, 2011.
4. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal,” Two Dimensional Analytical Subthreshold Swing Model of a Generic (3T- 4T) Double Gate MOSFET with Gate-S/D Underlap”, Proc. IEEE Int. conference on Electronic Devices, Systems and Applications (ICEDSA), Kuala Lumpur, Malaysia, pp. 246-249, 25 - 27 April 2011.
5. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal,” Two Dimensional Analytical Subthreshold current Model of a Generic (3T- 4T) Double Gate MOSFET with Gate-S/D Underlap”, Proc. IEEE Int. conference on Electronic Devices, Systems and Applications (ICEDSA), Kuala Lumpur, Malaysia, pp. 67-72, 25 - 27 April 2011.
6. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal,” “Analytical Potential Distribution Model for Underlap Double Gate MOSFETs with 3T-4T and Symmetric- Asymmetric Options for Subthreshold operation: A Conformal Mapping Approach”, Proceedings of Nanotech Conf & Expo (NSTI), Anaheim, California, USA, Vol.2, pp. 697-700, 21-24, June 2010.
7. Ramesh Vaddi, M.P. Shrivastav and Saroj Rangnekar, “Modeling and Simulation of Digital Governors of an automated Small Hydro plant using MATLAB- SIMULINK-dSPACE”, Proc. of International Conference on convergence of science and Engineering in Education and Research (ICSE-2010), Bangalore, India ,2010.
8. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal,” Robustness to PVT variations of Nano Scale Subthreshold CMOS Logic for Ultra Low Power Application “,Proc. of International Conference on convergence of science and Engineering in Education and Research (ICSE-2010), Bangalore, India ,2010.
9. Ramesh Vaddi, M.P. Shrivastav and Saroj Rangnekar, “SIMULINK Modeling and Simulation of an automated Small Hydro plant”, Proc. of International Conference on emerging trends in Energy and environment (ICETEE-2010), Chennai, India, 2010.
10. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, “Robustness Comparisons of bulk CMOS and DGFinFET technologies with Circuit Co-Design for Energy Efficient Subthreshold Logic “, IEEE International workshop on the Physics of Semiconductor Devices (IWPSD), New Delhi, India, Dec. 2009.
11. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, “Investigation of Robustness and Performance Comparisons of DG-FinFETs with Symmetric, Asymmetric, Tied and Independent gate options for Optimal Subthreshold Logic”, IEEE 4th International Conference on Computers & Devices for Communication (CODEC), Kolkata, India, 2009.
12. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, “SDG vs ADG with Tied and Independent gate Options in the Subthreshold Logic for Ultra Low Power Applications”, 2nd IEEE Int. workshop. on Electronic Devices and Semiconductor Technology(IEDST), IIT Bombay, India, June 2009
